Dr. Mohammed Feham and Dr. Mohamed Kameche also contributed to this article.

Frequency synthesizers are critical components in modern mobile-communications systems, powering both transmitters and receivers. Typically, they are designed with a phase-locked-loop (PLL) approach.¹ To demonstrate the effectiveness of this synthesizer architecture for one of the more challenging mobile wireless-communications formats, DCS1800, the authors designed and simulated a PLL frequency synthesizer for use in a DCS1800 base station. The base station operates in the receive band of 1805 to 1880 MHz and the transmit band of 1710 to 1785 MHz. The simulation considers the noise effects on each component in the frequency-synthesizer design and the impact of phase margin on system performance.

The frequency-synthesizer design consists of a phase-frequency comparator followed by a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and frequency dividers (Fig. 1). The charge pump converts the logic states of the detector into analog signals appropriate for controlling the VCO. In its off state, the charge pump and the input section of the synthesizer must exhibit extremely low leakage, otherwise voltage integration will occur at the loop filter between phase comparator events.

PLLs are most commonly used in frequency synthesizers, where a range of output frequencies is generated from a single stable reference frequency. This is done my means of a variable ratio divider in the feedback path. The frequency or channel to be synthesized is performed while acting on the ratio of division N (Fig. 1). Because its phase detector is nonlinear, a PLL is primarily considered a nonlinear device.

Figure 2 shows a linear mathematical model representing the phase of the PLL in its locked state,² where K_Ø is the phase detector/charge pump gain, Z(s) is the transfer function of the loop filter, N is the main divider ratio, and K_VCO is the gain of the VCO. The phase of the oscillator, θ₀, is compared with the reference, θ_r, and adjusted until the difference is zero. Parameters θ_i and θ_e are the opposite and the error phases, respectively.

The PLL phase-transfer functions are shown in Eqs. 1 and 2. The open-loop gain is:

The closed-loop gain is:

Since the design of the loop filter is the most critical part of the synthesizer, it will be the primary focus of this article.

The phase detector's outputs are associated with different signals by the charge pump. Each signal is applied to a lowpass filter so that the output voltage of the phase detector does not vary too quickly. Figure 3 shows the standard passive third-order charge-pump loop filter used in PLL frequency synthesizers. The lowpass filter effectively suppresses spurious signals produced by the phase detector so they do not cause unwanted frequency modulation in the VCO. The delay time of the filter, however, can result in degraded transient response and a limit in the switching speed of the frequency synthesizer.³

The transfer function of the third-order loop filter in Fig. 3 is given by:

where Z_fil2(s) describes the transfer function of the second-order loop filter given by:

If a temperature-compensated crystal oscillator (TCXO) is used in the PLL synthesizer design, the manufacturer's phase-noise data should be obtained so that reference values can be used with the models. Reference oscillator noise, N_tcxo(f), can be expressed by⁴:

The VCO noise can be modeled as a simple approximation inversely proportional to the offset frequency from the carrier. The noise of the VCO is effectively highpass filtered by the PLL, providing rejection of phase noise or phase error within the loop bandwidth, although VCO noise well outside of the loop bandwidth is unaffected. The VCO noise is given by⁵:

It should be noted that the noise generated by the lowpass filter's resistances can affect the input of the VCO even if the PLL is not connected (closed). Active devices, such as opamps, and resistors produce noise voltages. In the case of an operational amplifier, the noise should be specified. In the case of a resistance, this noise voltage is defined by the thermal noise produced by the resistance. The thermal noise produced by a resistance is:

where:

T₀ = the ambient temperature (equal to 300 K),
K = Boltzman's constant, and
R = resistance.

Figures 4 and 5 show, respectively, noise models for resistances R₂ and R₃ as being equivalent sources of noise voltage appearing in series with each resistance. Since the noise sources are not correlated, each resistance must be analyzed separately and the effects added afterward. The derivation of the real voltage of noise versus the input frequency at the VCO's tuning port is based on the basic circuit using models of Figs. 4 and 5.

The phase noise added to the output of the PLL by each resistance is given by the following equations:

where:

m_R2(f) = the modulation index according to the frequency for resistance R₂ and

m_R3(f) = the modulation index according to the frequency for resistance R₃.