Commercial and military satellites deploying Ka-band transponders are driving the need for high-performance L-band-to-Ka-band block upconverters (BUCs). These frequency translators will find use in portable and fixed terminals and must be compatible with both solid-state and tube-based amplifiers. To meet the needs of this growing market, Herley-CTI (www.herley-cti.com) has developed a low-phase-noise, dual-loop frequency synthesized BUC using dielectric resonator oscillators (DROs) to drive the local oscillator (LO). The compact BUC is based on computer-modeled mixer spurious analysis and filter designs and is manufactured with a low-cost approach that incorporates soft substrates, thick- and thin-film ceramic substrates, low-cost surface-mount components, and wire-bonded monolithic microwave integrated circuits (MMICs) all in the same assembly.

The L-to-Ka-band BUC takes advantage of several different high-frequency circuit technologies and the latest computer-aided-engineering (CAE) programs to predict and optimize the performance of its component parts. The BUC consists of four major sections, including the input diplexer and intermediate-frequency (IF) amplifier/gain-control chain; the mixer, upconverter mixer, filter, and amplifier chain; low-phase-noise, dual-loop LO; and DC power supply, bias, and control board (Fig. 1).

The BUC's IF input contains the 10-MHz reference multiplexed with the 1-to-2-GHz information signal. The IF signal is demultiplexed at the input diplexer, which separates the two signals. The 10-MHz reference signal from the diplexer is split and sent to the 14.5-GHz LO phase-lock board and also to the DC power supply, bias, and control board. The 1-to-2-GHz signal from the diplexer is preamplified and passed through a temperature-compensation/gain-slope equalizer circuit and second amplifier/temperature-compensation circuit. The second IF amplifier is followed by a digital attenuator for user-selectable gain and a variable analog attenuator for further temperature compensation. The conditioned IF signal is then fed to the millimeter-wave section, where it is upconverted, filtered, and amplified to the final output level at 30 to 31 GHz.

The low-phase-noise, dual-loop LO section consists of a 14.5-GHz, GaAs-MESFET-powered, voltage-tuned dielectric resonator oscillator (VTDRO) that is phase-locked via a sampling loop to a low-noise 100-MHz voltage-tuned crystal oscillator (VTXO). The VTXO is phase locked via a digital phase-locked loop (PLL) to a customer-supplied 10-MHz reference oscillator. The DC power supply, bias, and control board includes all of the circuitry necessary to filter the input voltage signal, generate and control the bias voltages for the various stages, monitor temperature, and control the gain-compensation circuits. Figure 2 shows a block diagram of the DRO used as the LO in the BUC.

The PLL acts as a lowpass filter for the multiplied reference phase noise and as a highpass filter for the locked oscillator phase noise. The LO design incorporates a digital loop to lock the VCXO to the 10-MHz reference source. The digital PLL chip's phase-detector frequency is programmed to 2.5 MHz in order to achieve low spurious content and good phase noise. A loop bandwidth of 100 Hz was chosen to track the long-term stability of the reference and take advantage of the low noise of the VCXO. The phase-locked VCXO exhibits a noise floor of better than –165 dBc/Hz at offsets greater than 10 kHz from the carrier. To take advantage of this low-noise performance, the PLL noise floor of the sampling loop must be equally low. Otherwise, it will limit the noise inside the loop. The sampling PLL has been shown to exhibit a phase-noise floor of –165 dBc/Hz with a 100-MHz phase-detector frequency—a suitable choice for low-noise applications.¹

Equally important to the performance of a sampling PLL is the design of the reference amplifier. The reference amplifier on the input of the sampling PLL must not degrade the reference phase noise. The reference amp must also maintain a constant signal level to the phase detector over variations in temperature and reference level. Through the use of proprietary sampling PLL circuitry, the LO provides exceptionally low phase noise, typically –111 dBc at 10 kHz offset from the 14.5-GHz carrier. Adding 6 dB doubling noise due to the subharmonic mixer, this projects to a phase noise of –105 dBc/Hz offset 10 kHz from the 29-GHz LO. The proprietary low-noise loop architecture, along with the low phase noise of the VTDRO, permit the use of a wide sampling loop bandwidth of about 300 kHz. The wide loop bandwidth yields low microphonics and operation free of phase hits—two critical performance parameters in both commercial and military satellite-communications systems.

Since a 14.5-GHz fundamental oscillator is used for the LO, the far-from-the carrier noise floor of this oscillator is exceptionally low, generally below –150 dBc/Hz at offsets greater than 10 MHz. This noise floor is significantly better than units that use multiplied L-band oscillators where the noise floor is degraded by the 20logN multiplication (with N the multiplication factor). Figure 3 shows a plot of the phase-noise performance for the 14.5-GHz dual-loop, phase-locked DRO locked to a 10-MHz low-noise crystal reference oscillator.

A key to the successful design of any upconverter is effective mixer spurious analysis. The analysis must accurately predict the spurious signals that will appear at the output of the mixer due to the upconversion process. Any signals that fall outside of the required passband must be identified and appropriately filtered to fall below acceptable levels.

In addition, any mixing products that fall within the band of interest must be identified and minimized through a combination of proper choice of mixer and design of the signal level present at the input to the mixer. Adjustment of signal levels inevitably leads to the system trade-off between spurious levels and usable dynamic range. Simulations were performed to create a plot of spurious products present at the output of the mixer with a 1-GHz input at –15 dBm. The simulations revealed that spurious signals can be expected at 27, 28, 29, and 31 GHz. The 29-GHz bleed-through signal is independent of the IF input signal and, as the spurious signal closest to the passband, defines the rejection requirement of the filter following the mixer. The 31-GHz signal is the product of the 29-GHz LO and twice the IF of 1 GHz. Since this signal falls inside the passband of the upconverter output, it cannot be filtered out. In order to lower this spurious signal, the signal level at the input to the mixer must be lowered. Since this is a third-order spurious product, the spurious level will drop 3 dB for every 1 dB the input level to the mixer is dropped.

Once mixer analysis has been performed, the filter requirements can be defined. After examining the spurious response calculations, it was determined that the 29-GHz signal output of the mixer must be lowered by 85 dB. To meet the performance and cost requirements, a seven-pole edge-coupled filter topology manufactured on 7-mil polished alumina was selected.

Figure 4 shows simulated rejection, insertion loss, and return loss for the proposed filter. Three different graphs are over-laid, showing the worst-case predicted movement of the filter due to temperature and manufacturing tolerances. To meet the demanding rejection requirements, it was necessary to cascade two filters in the final BUC design. Figure 4 shows the simulated group delay of the filter.

Measurements were made of the spurious signals present at the output of the BUC with a 1-GHz input signal at –15 dBm feeding the BUC and with the two filters placed after the mixer in the upconverter amplifier chain. To prevent interaction between the filters, the final design incorporates a 3-dB attenuator following the mixer and dual seven-pole filters separated by an isolation amplifier stage. The measurements showed that the 31-GHz spurious signal has been reduced by 6 dB by lowering the input level to the mixer by 3 dB.

The BUC design includes circuits on soft board, thick- and thin-film ceramic substrates, surface-mount components, and wire-bonded MMICs within the same integrated assembly. Standard components are used whenever possible. The best technology for a particular function is selected in terms of cost, manufacturability, and performance. The BUC housing incorporates an H-frame style with LO, IF, and millimeter-wave sections on one side and a low-cost, plug-in control board on the back side.

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