Frequency synthesizers orchestrate the frequency translation in modern wireless transceivers. The performance of the synthesizer, notably its phase jitter and spurious levels, can greatly determine the performance of the overall wireless system. Many factors impact phase jitter and spurious, including the choice of synthesizer architecture—integer-N or fractional-N phase-locked loop (PLL)—and the number of loops and comparison frequency. Synthesizers typically consist of a voltage-controlled oscillator (VCO), prescaler, programmable divider, digital control logic circuitry, phase-frequency detector (PFD), charge pump (CP), and loop filter. By focusing on two of the key synthesizer components, the PFD and CP, synthesizer phase jitter and spurious performance can be improved.

Typically, a PFD has two inputs and two outputs. The device normally consists of two D-type flip-flops (DFFs) and reset logic circuitry. One input is for the reference frequency signal while the other is for the divided VCO signal, and the phase difference between the two is compared in the PFD. A difference in phase results in a pulse generated at either the UP or DOWN output of the PFD. Ideally, the pulse width is linearly proportional to the phase difference.

The CP consists of a current sink, a current source, and their corresponding switching networks. The UP/DOWN pulse controls how long the CP will source or sink the current to the loop filter. Figure 1 shows a typical PFD and CP circuit. An inverter is inserted to make sure the correct polarity if the current source is implemented with PMOS.

The operation of the circuit can be readily understood by assuming that f1 and f2 are zero at the start. A clock transition at f1 will trigger the upper DFF to a logic high state. The current source then begins to inject current to the loop filter. When the f2 input experiences a clock transition, the DOWN output will be in a logic high state. The NAND gate is the reset circuit that will generate a logic low to reset both DFFs. The current source is shut off and a pulse corresponding to the phase difference between f1 and f2 is generated. This is for the case where f1 leads f2, but a similar process applies for when f1 lags f2 where a pulse at the DOWN path is generated and NMOS is turned on to sink the current from the loop filter.

The most popular implementation of a conventional PFD involves standard logic cells (Fig. 2). In this case, elements U2 and U3 form the top-half DFF while U4 and U5 complete the bottom DFF. The four-input NAND generates the reset signal. The rest of the circuitry includes buffers/delay cells (for combating the dead-zone problem) and polarity-inverting buffers. This is an often-used, robust topology, although its speed is limited by the propagation delay in the reset path of the logic gate. In addition, its frequency-detection performance is not optimized. F1 must be 10 times faster than F2 in order for this PFD to clamp to the highest control voltage of the VCO.

Simplicity is a key to faster synthesizer speed. By using the faster and simpler logic like the True Single Phase Clock (TSPC), the DFF can be implemented with just a few transistors instead of a few gates. Figure 3 shows a popular implementation of this approach. Transistors M1 through M9 form the upper latch, while transistor M11 through M19 form the bottom latch; both latches are identical. The field-effect transistors (FETs) M1 through M6 basically represent a modified version of a standard doubled n-CMOS latch using a precharge technique.

The theory of operation for the latch is straightforward, based on the assumption that f1 and f2 are both a logic low states at the start. Node A is precharged to a logic high state. As f1 makes the transition from a low state to a high state and f2 stays low, device M5 is turned on and transistor M5 turns on the inverter formed by transistors M4 and M6. Node B is pulled low. Transistors M7 and M8 form an inverter to generate the UP signal. Transistor M9 is added to fix one special problem in this architecture. Because of normal mismatch in delay between the top and bottom latches, the difference between the latches results in a narrow pulse for both the UP and DOWN outputs even when no input phase difference exists. With M9, node A is discharged to ground (GND). As f1 rises from low to high, node B is pulled up to a logic high state (H) and the UP output will be pulled down to a logic low (L) state. The bottom latch works in the same way.

Compared to a traditional PFD, there is no feedback reset logic circuitry required in this simple approach (Fig. 3). Reset delays are short, and a PFD using the TSPC implementation provides much higher operating frequencies than conventional PFD approaches, with operating frequencies in the low gigahertz range reported by many researchers. Although the implementations for TSPC are only briefly covered in this article, it is an extremely flexible logic family with many variations possible.

Figure 4 shows a second implementation of TSPC for a PFD compared to Fig. 3. The latch in Fig. 4 works as follow. With reset and f1 initially at a logic low state, transistors M1 and M2 are turned on. The drain of M3 is precharged to a logic high state. A rising edge at f1 will turn on device M5. Since M3's drain is precharged to a logic high state, M4's drain will be at a logic low state. It is then inverted to generate the UP signal. The bottom latch is identical to the top latch. Since both latches produce the inverse of the desired logic outputs, a NOR gate is used instead of a NAND gate. The circuitry in Fig. 4 is closer to a conventional PFD architecture than that in Fig. 3. The major difference between Figs. 4 and 3 is how the reset signal is generated.

Two DFFs can be added to improve the frequency pull-in speed. These help clamp the control voltage even when f2 is only two times the frequency of f1. Figure 5 shows a typical implementation of this enhanced approach, which also requires two additional OR gates.

Overcoming the "dead zone" is a well-known problem in PFD design. For an ideal PFD, the phase response can be thought of as a line traveling through the origin, with input phase range from –2p to +2p and slope equal to the gain of the PFD. In a less-than-ideal PFD, there is a dead zone with no gain, resulting in the slope of the line being flat near the origin. In a dead zone, a synthesizer will temporarily lose lock. The phase noise will accumulate until it is large enough to exist outside of the dead zone, and the phase jitter performance will be degraded.

The dead zone is due to the finite turn-on/turn-off time of the switch in the CP and the time it takes to charge/discharge the loop-filter capacitor. As f1 and f2 are closer in frequency, the turn-on/turn-off pulse becomes narrower. If the CP can't switch fast enough, the DFF will be reset before the CP can even charge/discharge the loop filter. A solution is to add intentional delay in the reset path. The delay must be long enough for the CP to avoid the dead zone and short enough to meet the upper operating frequency requirements.

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