Reliable GaAs-based optoelectronic devices, such as GaAs/InGaAs quantum well lasers, can be realized on silicon substrates using several advanced techniques. Fabrication involves first forming germanium (Ge) stripes on a silicon dioxide (SiO₂) trench-patterned silicon substrate via aspect ratio trapping (ART), where any defects originating from the Ge/Si interface are trapped by laterally confining sidewalls. Defects arising from above the SiO2 film are reduced by means of an optimized epitaxial lateral overgrowth (ELO) process followed by chemical mechanical polishing (CMP) to provide a planar Ge surface. Then, a GaAs/InGaAs laser structure is overgrown on the virtual Ge substrate. This new fabrication method overcomes traditional problems plaguing GaAs/Ge integration, including Ge autodoping and antiphase domain defects in GaAs.

In recent decades, much effort has been made to fabricate electronic and optical devices on GaAs/Si.^1-6 However, major problems remain unresolved, in particular, the high density of threading dislocations in GaAs layers grown directly on Si due to the 4-percent lattice mismatch and the difference in the coefficient of thermal expansion (CTE) between the two materials. The threading dislocations act as nonradiative recombination centers in optical devices and lead to device performance degradation. To date, significant progress has been made in reducing GaAs dislocation density for material growth by employing various epitaxial schemes such as cycle thermal annealing,⁴ epitaxial lateral overgrowth,⁵ and growth on compositionally graded SiGe buffers.⁶ However, these methods generally require relatively thick epitaxial layers and/or high-temperature annealing steps, which may complicate integration with Si-based integrated circuit technologies.

Ge is an ideal intermediary material between GaAs and Si because of its complete miscibility with Si and its close lattice match with GaAs at room temperature.⁷ Recently, the current researchers demonstrated low-defect Ge and GaAs materials grown in SiO₂ trenches on Si via the ART method,^8,9 where threading dislocations arising from lattice mismatch are trapped at vertical sidewalls confining the growth region. Full trapping of dislocations has been demonstrated for trenches to 400 nm in width without the formation of additional defects at the sidewalls above 250 nm initial growth. Although misfit dislocations are fundamentally unavoidable, they may be inconsequential to device performance if they can be trapped within a thin layer near the Ge/Si or GaAs/ Si interfaces, away from the device active region. In fact, ART-based high-performance Esaki diodes¹⁰ and MOSFET¹¹ devices using monolithically grown GaAs/ Ge/Si structures have been successfully demonstrated.

This article reports on 980-nm GaAs/In- GaAs lasers grown on virtual Ge substrates, for which the Ge thin film was grown on Si (001) substrates via the ART method followed by CMP. The laser diodes are uncoated edge-emitting broad-area devices. Despite the fact that unoptimized laser structures have relatively high series resistance and large threshold current densities, this ART-based approach provides a promising pathway with several unique features in achieving high-performance III-V devices on Si. The approach allows misfit-defectinduced threading dislocations in Ge to be essentially trapped within a limited layer thickness inside SiO₂ trenches via ART.⁸ The density of coalescence defects, which have been seen to be the major cause during coalesced growth,¹² can be dramatically reduced by enhancing ELO, through which large-area, low-defect Ge can be obtained. GaAs overgrowth on the polished planar Ge surface enables further reduction of threading defects with buffer layer optimization at GaAs/ Ge interface. On-axis Si (001)-based virtual Ge substrates created by the ART + ELO growth process possess off-cut surface characteristics, which lead to antiphase domain (APD) reduction in overgrown GaAs.

The substrates used in this study were 200-mm-diameter ptype on-axis Si (001). A thin SiO₂ layer was thermally grown on the Si substrate, followed by conventional photolithography and reactive ion etching (RIE) techniques to form multiple sections of trenches and waffle patterns, exposing the Si surface along the [110] direction. Each section has a 0.25-µm trench width. The SiO₂ spacer between neighboring trenches varies from 0.25 to 20 µm in the various trench sections, while sections were separated by 10 µm of SiO₂. After wafer preparation and prior to growth, the final trench height was about 480 nm.

Two-step low-pressure MOCVD processes were performed in this study. First, an epitaxial Ge layer was grown on the patterned substrate under optimized growth conditions similar to that described previously.⁸ Ge growth was terminated after the Ge layer slightly coalesces in the 20- µm spacer section (later referred to as the ELO section), which corresponds to an average layer thickness of about 4 µm. Then, a CMP process was used for planarization of the Ge-SiO₂ composite structure.¹³ Before GaAs overgrowth, the polished Ge/Si substrate was cleaned with successive dips in H₂O₂ solution and 1:50 diluted hydrofluoric (HF) acid, with deionized water rinses between steps. In the second growth step, GaAs layers were deposited in a separate MOCVD reactor at constant low pressure (70 Torr) by using triethylgallium (TEG) and arsine (AsH₃) for buffer layer growth and trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMI), and AsH₃ for upper structural layer growth. Prior to buffer layer growth, the wafer was baked at +600°C for 10 minutes under H₂ overpressure followed by 2 minutes of As-coating by introducing AsH₃ overpressure. Then the growth temperature was reduced to +400°C for 30-nm GaAs buffer layer growth followed by a three-period GaAs (10 nm)/Al_0.4Ga_0.6As (15 nm) superlattice structure grown at +600°C. Finally, an n-type GaAs base layer and 980 nm GaAs/InGaAs laser structure were grown using various growth temperatures. The laser structural growth rates were kept at 7 nm/min for the buffer layer and 50 nm/min for the top layers. Carbon tetrabromide and SiH3 were used for p- and n-type doping, respectively. Each growth run contained both a GaAs (001) substrate and Ge (001) substrate, in addition to the Ge ART virtual substrate, for comparison.

The virtual Ge ART substrate was examined by optical Nomarski microscopy before GaAs overgrowth. These post-CMP wafers showed smooth surface morphology in all sections except the ELO trench section, in which linear depressions existed due to incomplete coalescence of the Ge film over the oxide spacer. After GaAs overgrowth, the surface looked very smooth in the scanning electron microscope (SEM) on all sections except the ELO section, which retained the pregrowth Ge surface feature. Cross-sectional SEM images of the laser structure are shown in Fig. 1. Figure 1(a) was taken from a trench-patterned section with 10-µm SiO2 spacer while Fig. 1(b) was from the ELO section. In Fig. 1(c), the top-view SEM of the ELO section indicated that the overgrown film coalesced with a variable facet, suggesting that the linear depression must be removed or electrically isolated for laser device fabrication.

Room-temperature photoluminescence (PL) mapping was conducted for lasers grown on multisection virtual Ge ART substrate using a 514-nm argon (Ar) laser for optical excitation at 30 mW output power. Since the GaAs cap layer has strong absorption of the laser line, the GaAs cap layer was etched off under identical etching conditions, for all inspected samples, before PL measurements. Mapping results showed that the ELO section demonstrated the best PL characteristics of all the patterned sections, which confirmed the results obtained from etch pit density (EPD) analysis on virtual Ge ART substrates, from which the lowest etch pit density has been demonstrated from ELO regions.¹⁴ In Fig. 2, single PL spectrum results measured from the 1-µm spacer section and ELO section are compared to those grown on GaAs and Ge substrates. All samples were grown under the same conditions. The figure shows that the PL peak intensity measured from the ELO section is about 60 percent that on a GaAs substrate, but is three times higher than that on the 1-µm spacer section, as well as about five times higher than that on a Ge (001) substrate. This implies that the material quality varies depending on the initial ART mask pattern with which the Ge layer was grown. Although the uncoalesced ELO section demonstrated the best epitaxial quality by PL, the laser diodes were fabricated and tested from the fully coalesced 1-µm spacer section because its planar surface allowed more straightforward laser device fabrication.

The key step for achieving highperformance lasers on a Ge substrate is the growth of a low-defect GaAs transitional base layer, which is designed as a lateral n-type conduction layer for laser diodes. Without deliberate growth optimization, issues related to antiphase domain (APD) and Ge contamination in GaAs may severely degrade or even destroy the overgrown device performance.^15-19

In this case, because the Ge film was grown on exact (001)-oriented Si substrates, APDs become a primary concern due to the well-recognized polarity mismatch (polar/non-polar) at the GaAs/Ge interface. Fortunately, growth calibration revealed that the tendency of APD formation on a virtual Ge ART substrate surface is different from that observed on a Ge (001) substrate. The current researchers found that APDs can be effectively avoided using an optimized GaAs/AlGaAs superlattice structure for growing GaAs on virtual Ge ART substrates. As seen in Fig. 3(a), the high-density antiphase disordered networks appeared as expected in the 2-µm GaAs base layer grown on an on-axis Ge (001) substrate. However, the same base layer grown on the virtual Ge ART substrate is nearly free of APDs as shown in Fig. 3(b). This can be attributed to APD reduction to the crystallographic growth behavior of the Ge grown on Si via ART.²⁰

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