Direct-digital synthesizers (DDSs) are flexible integrated circuits (ICs) capable of answering a host of design challenges. Programmable DDS ICs are agile frequency sources capable of low phase noise and good spurious performance. Until now, DDS performance has been saddled with a trade-off between clock rate or tuning resolution and power consumption. But the new 9954 DDS IC and other members of the 995X DDS families offer maximum update rates to 400 MSamples/s without turning up the power—only 180-mW power is consumed for the 9954 at 400 MSamples/s. The new DDS ICs are well-suited for frequency-agile frequency-shift-keying (FSK) and phase-shift-keying (PSK) modulators, as well as radar applications and any other commercial and military designs requiring fast-switching speeds with high frequency resolution and low phase noise.

The flagship of the new DDS product line is the model AD9954, with swept-frequency capabilities, precise amplitude control, multiple profile selection, on-chip 1024 × 32-b random-access memory (RAM), and an integral 14-b digital-to-analog converter (DAC). The IC also includes a phase-locked-loop (PLL) clock multiplier, on-chip crystal oscillator, and a high-speed comparator. Despite its functionality, the AD9954 is designed to operate on a mere +1.8 VDC. A 32-b phase accumulator at the heart of the AD9954 DDS core (Fig. 1) provides fine tuning resolution (0.093 Hz for a 400-MHz clock). Essentially, a DDS constitutes a sophisticated numerically controlled oscillator (NCO) that works by incrementing in a controlled manner a value representing the phase of a sinusoidal waveform. The phase accumulator acts as a modulus M counter and adds a delta-phase word to the existing phase with each clock cycle. The average rate at which the phase accumulator overflows determines the frequency of the generated signal and depends on the magnitude of the delta-phase word. The frequency is derived from the system-clock frequency and the capacity of the phase accumulator (2³²) according to the formula f₀ = (Tf_s) /2³², where:

T = the value of the frequency tuning word or delta-phase word (0 ≤T ≤2³¹),
f₀ = the output frequency, and
f_s = the system clock frequency.

Changing the frequency-tuning word of a DDS results in a phase-continuous output frequency that changes immediately. The addition of the phase-offset register provides further control of the accumulator and is a means to shift the phase of the output sinusoid under digital control. The output of the phase accumulator does not directly represent the amplitude of a sine wave. Therefore, following the phase accumulator, a phase-to-amplitude conversion circuit, represented by the cos(x) block in Fig. 1, processes the phase-accumulator result. The output of the phase-to-amplitude conversion represents a digital sine wave that the DAC converts to an analog signal. The phase accumulator generates the digital signal with 32 b of phase information, resulting in a tuning resolution of less than 1 Hz.

The 32-b phase accumulator yields far more phase resolution than can be resolved by a 14-b DAC. If all 32 b representing phases were converted to amplitude, an enormous amount of logic would be required. Therefore, to reduce circuit complexity and to save die area and power, designers commonly truncate the phase information before presenting it to the phase-to-amplitude conversion logic. Truncation leads to a systematic phase error in the signal and the error shows up in the DDS spectrum as spurious energy. The accumulator size, the phase word after truncation, and the tuning word determine the magnitude of these spurious products. As long as the spurious-free dynamic range limitation due to these spurious products remains below that afforded by the DAC, the DDS core does not become a performance restraint. Although the DDS generates frequencies with the 32-b phase accumulator to achieve high tuning resolution, much of the least-significant-bit (LSB) information is superfluous to the DAC. Since the DAC limits spurious performance to a 14-b level, the phase information can be safely truncated without loss of performance. The result is a highly tunable frequency generator with the ability to switch from one frequency to another almost instantaneously, while maintaining continuous phase and good spectral performance. In addition to its high resolution, the AD9954 includes dithering of the signal phase to improve the spurious performance at offsets close to the output frequency. The randomization of the LSBs of each phase word reduces spurious signal power due to the phase truncation that occurs just before the cos(x) block converts the phase.

The AD9954 includes 1024 × 32-b RAM, which can be powered down when not required for an application. When enabled, the RAM's output drives either the phase accumulator or the phase-offset adder. When the RAM drives the phase accumulator, users provide frequency-tuning words through RAM addresses and control the phase of the output by programming the phase-offset register. Programming the RAM to drive the phase-offset adder means the contents of the frequency-tuning-word register sets the DDS output frequency and the contents of the RAM determine its phase. The ability to choose where the RAM contents go makes programming the DDS for PSK modulation nearly identical to FSK modulation. Additionally, the RAM can be separated into four distinct addressable segments, enabling symmetrical or nonsymmetrical phase and frequency sweeping.