Design time can be dramatically shaved with the help of a new simulation technique that enables RF designers to perform root-cause analysis of RF architectures. The approach provides complete spectrum identification and origination information for each design, and allows arbitrary topologies and multiple signal paths to be explored. Based on a single software tool, continuous verification from the RF architecture phase through the measured data phase can now be performed.

When developing an RF architecture, an engineer determines the type, number, and order of stages needed to meet a set of requirements. Spreadsheets such as Microsoft Excel have typically been used for this design task, but the approach is inexact and can lead to a poor RF architecture which will then present problems and lead to long product-development cycles. Design cycles typically occur when the basic RF architecture must be modified, or because an electromagnetic (EM) analysis has uncovered unwanted field effects. Although design cycles due to EM problems are sometimes unavoidable (or at least unforeseen), design cycles due to poor RF architectures can be virtually eliminated with this new simulation technique.

An effective software tool for RF architecture analysis should at the least:

• Provide RF root cause analysis;
• Perform design verification at every step in the design process (users should be able to substitute designed and measured circuits into the architecture);
• Provide channel measurements at any frequency;
• Analyze channel measurements along arbitrary paths;
• Analyze "sneak" or leakage paths;
• Account for nonlinear behavior;
• Simulate broadband noise;
• Provide architectural optimization; and
• Simulate conducted emissions.

These features are part of a new simulation technique implemented in the SPECTRASYS module of the GENESYS suite of RF design software tools from Eagleware Corp. (Norcross, GA).

An example may help to illustrate how effective RF architecture analysis can save design time, using a three-sector 5.8-GHz wireless-local-area-network (WLAN) VSWR/power tester (Fig. 1). In this design, a switchable receiver measures forward and reflected power for each of three antennas. The impedance of each antenna has been defined in terms of return loss. The first intermediate frequency (IF) is 450 MHz with no automatic-gain-control (AGC) stage. Consequently, this output can be used for actual power measurements. The second IF is at 70 MHz and has AGC. The second IF can be used as a demodulated output.

Figure 2 shows a WLAN modulation source applied to each antenna through a coupler. A virtual node has been created between antennas to represent antenna-to-antenna isolation. In this example, the dynamic range of the WLAN input signal is assumed to be between +10 and +30 dBm. This tester must accurately measure VSWR across this dynamic range for both the forward and reflected power.

The high-power case occurs when looking at the forward power of +30 dBm. Figure 3 is a level diagram showing the total node power compared with the 1-dB compression point for each node, indicating that the last amplifier is in compression (the schematic symbol also changes color indicating an error). The graph makes helps to identify all of the weak links in this headroom chain.

The low-power case occurs when looking at the reflected power at the input power of +10 dBm. Figure 4 shows a level diagram showing the total power at the node compared to the power in a 22-MHz WLAN channel. By examining the total power at that point (the anticipated channel power), rather than with a power meter placed at the output port, a problem signal becomes apparent.

Once a problem is known, the next step is finding the root cause of the problem. By checking the first IF output spectrum in Fig. 5, the offending signal can be identified at a frequency of 380 MHz, power level of +1.936 dBm, equation of [SigLO2] (which is the name of the second LO source), a creating element of "Port8," and a traveled path to the viewing node. The root cause of the problem is the second LO signal leaking into the output of the first IF section.