Key EDA tool requirements for RF/baseband system design
EDA tool attribute	Simulation requirement
Hierarchical system/circuit representation in a common environment	Needed to verify circuit interaction effects on WLAN system performance and provide an implementation path.
Synchronous timed data-flow manager	Provides a basis for a plug-in framework tool, that can interact with other EDA tools and data sets. Agilent Ptolemy is an example of one such data-flow manager.
Multi-platform support	For maximum flexibility, support for popular Unix and PC platforms facilitates maximum inter-tool connectivity and compatibility with user CAE hardware.
Analog/digital functional blocks and propagation models	Needed to perform full system-level simulation of RF with analog/digital components.
System/HDL co-simulation	Provides basis of IP (intellectual property) re-use and utilization of custom behavioral models. Provides vectors for bottom-up verification of RTL.
Floating-point simulation	Fast simulation, with a wide array of block and propagation models specifically tailored for the WLAN application.
True fixed-point modeling	True fixed-point simulation provides accurate results for implementing systems like WLAN. Be careful of truncated fixed-point emulation, which is not the same, and sacrifices accuracy. For WLAN systems, higher order bit precision of "2.12" or higher may be required.
RF circuit-block verification	Provides a high abstraction level for basic, steady state RF/AMS behavioral block simulation. Behavioral block models extracted from actual circuit implementation is desirable for fast validation of circuit performance.
System/circuit co-simulation	Provides a means to verify circuit-level time varying performance and physical design effects on system performance. Designers need Circuit Envelope and/or SPICE/convolution to perform effective system/circuit co-simulation to a detailed level.
High-performance harmonic balance engine for co-simulation	Simple steady-state analysis using harmonic balance simulation may still require the ability to handle four or more subcarriers, with multiple harmonics and spurious responses. Krylov solvers and transient assist will speed simulation time and provide better convergence, especially for large circuits used in today's wireless systems.
Time- and frequency-based simulation and modeling capability at the system and circuit level	Frequency-based simulation is needed to determine fast and accurate EVM, ACPR, and spurious results. Both the system- and circuit-analysis tools must have time-based simulation capability to handle the complete implementation of PLLs, AGCs, oscillator stability, switching time, modulators/demodulators etc. Less capability may not catch dynamic circuit problems.
Circuit Envelope simulation	Used to perform circuit-level simulations involving time varying complex modulation. This is the only simulation technology that allows simulation of circuits (as opposed to behavioral models) with time-varying complex modulation.
Tailored application test benches	Fully coded BER, PER, EVM, ACPR are examples of tests that if tailored to the WLAN application, permitting full verification of a design to a communications standard. Test benches provide an easy test environment.
Integrated system/circuit design environment	Provides a common platform with a familiar "look and feel" for system, circuit, and baseband designers, to obtain maximum efficiency in design and verification.
Hierarchical optimization	Provides the capability to optimize circuit-level attributes to obtain best system-level performance.
Yield analysis/Design Centering	If used at both the system and circuit level, these tools can optimize production yield.
EM analysis	Model physical design, isolation, signal contamination (crosstalk and other coupling effects).
Connected simulation/instrumentation solutions	Provide unique solutions to difficult problems. Provides a means of testing EDA designs with external hardware like power amplifiers designed for WLAN applications. Performs a powerful and unique de-bugging capability.
Hierarchical optimization	Provides the capability to optimize circuit-level attributes to obtain best system-level performance.